The aim was to realize and use PCM measurement on full wafer scale to evaluate different influences on the interconnect performance.

In detail the e-plating conditions as well the lithography parameters had to be adjusted to cover step heights of 2…18µm. As shown in the picture, the topology on the test chips were covered well. The first measurements and results were presented at the technical meeting in Halle. In general the measured resistances fit quite well to the calculated values. On the basis of these investigations we will apply the processes (e.g. Cu-e-plating) on printed chiplets on target wafer scale during next month.