| About MicroField
Copper Redistribution Layers (RDLs) are fundamental to advancing modern semiconductor packaging, enabling the intricate wiring required for complex chip architectures and heterogeneous integration. The development in this area focuses on achieving higher interconnect densities and improved electrical performance, crucial for applications demanding increased bandwidth and reduced latency. Technological strides are being made in creating finer copper traces and spaces, often through advanced lithography and deposition techniques, whilst simultaneously addressing challenges such as electromigration and reliability. This progress is not only driven by the need for smaller form factors in smart devices and advanced computing but also by the desire to facilitate novel integration schemes like chiplets and stacked architectures, where efficient interconnections are paramount for overall system functionality and performance. Beyond traditional wafer-level processing, the exploration of alternative fabrication methods, such as micro-transfer-printing for precise placement of copper interconnects, offers new avenues for RDL development. This approach holds promise for enabling on-demand connectivity and creating bespoke interconnect patterns that might be difficult to achieve with conventional methods. The successful implementation of advanced Cu-RDLs is intrinsically linked to robust chip design methodologies that account for their unique electrical characteristics and to rigorous testing protocols that validate their performance and reliability under demanding operating conditions. Ultimately, advancements in copper RDL technology are a critical enabler for the next generation of smart systems, pushing the boundaries of what is possible in terms of miniaturisation, power efficiency, and functional integration within microelectronic devices. |
Cu-RDL development
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23 October 2019
by Super User
The objective was to implement and utilise phase-change memory (PCM) measurements across an entire wafer. This approach allows for a comprehensive assessment of various factors impacting interconnect performance within semiconductor devices. By examining the wafer-scale behaviour, we can gain deeper insights into how different processing steps or material variations affect the electrical characteristics of these critical interconnections.
Extensive adjustments to the electro-plating conditions and lithography parameters were necessary to successfully address significant step heights ranging from 2 to 18 micrometres. As visually confirmed, the complex topography present on the test chips was uniformly and effectively covered. Initial measurements and findings were subsequently presented at an internal technical review meeting. Overall, the measured electrical resistances demonstrated a commendable alignment with the theoretically calculated values. Building upon these comprehensive investigations, the developed processes, including copper electro-plating, are slated for application to printed chiplets on target wafer substrates within the coming month.
